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INTEGRATED CIRCUITS
74LVC16374A/74LVCH16374A 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State)
Product specification Supersedes data of 1997 Aug 22 IC24 Data Handbook 1998 Mar 17
Philips Semiconductors
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State)
74LVC16374A/ 74LVCH16374A
FEATURES
* 5 volt tolerant inputs/outputs for interfacing with 5V logic * Wide supply voltage range of 1.2 V to 3.6 V * Complies with JEDEC standard no. 8-1A * CMOS low power consumption * MULTIBYTETM flow-through standard pin-out architecture * Low inductance multiple power and ground pins for minimum
noise and ground bounce
PIN CONFIGURATION
1OE 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 1 2 3 4 5 6 7 8 9 48 1CP 47 1D0 46 1D1 45 GND 44 1D2 43 1D3 42 VCC 41 1D4 40 1D5 39 GND 38 1D6 37 1D7 36 2D0 35 2D1 34 GND 33 2D2 32 2D3 31 VCC 30 2D4 29 2D5 28 GND 27 2D6 26 2D7 25 2CP
* Direct interface with TTL levels * All data inputs have bus hold (74LVCH16374A only) * High impedance when VCC = 0
DESCRIPTION
The 74LVC(H)16374A is a 16-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus oriented applications. The 74LVC16374A consists of 2 sections of eight positive edge-triggered flip-flops. A clock (CP) input and an output enable (OE) are provided for each octal. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. These features allow the use of these devices in a mixed 3.3V/5V environment. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The 74LVCH16374A bus hold data inputs eliminates the need for external pull up resistors to hold unused inputs.
GND 10 1Q6 11 1Q7 12 2Q0 13 2Q1 14 GND 15 2Q2 16 2Q3 17 VCC 18 2Q4 19 2Q5 20 GND 21 2Q6 22 2Q7 23 2OE 24
SW00074
QUICK REFERENCE DATA
GND = 0V; Tamb = 25C; tr = tf 2.5 ns SYMBOL tPHL/tPLH fMAX CI CPD PARAMETER Propagation delay Cp to Qn Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop VCC = 3.3V1 CL = 50pF VCC = 3.3V CONDITIONS TYPICAL 3.8 150 5.0 30 UNIT ns MHz pF pF
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL x VCC2 x fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES 48-Pin Plastic SSOP Type III 48-Pin Plastic TSSOP Type II 48-Pin Plastic SSOP Type III 48-Pin Plastic TSSOP Type II TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74LVC16374A DL 74LVC16374A DGG 74LVCH16374A DL 74LVCH16374A DGG NORTH AMERICA VC16374A DL VC16374A DGG VCH16374A DL VCH16374A DGG DWG NUMBER SOT370-1 SOT362-1 SOT370-1 SOT362-1
1998 Mar 17
2
853-2028 19111
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State)
74LVC16374A/ 74LVCH16374A
PIN DESCRIPTION
PIN NUMBER 1 2, 3, 5, 6, 8, 9, 11, 12 4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42 13, 14, 16, 17, 19, 20, 22, 23 24 25 36, 35, 33, 32, 30, 29, 27, 26 47, 46, 44, 43, 41, 40, 38, 37 48 SYMBOL 1OE 1Q0 to 1Q7 GND VCC 2Q0 to 2Q7 2OE 2CP 2D0 to 2D7 1D0 to 1D7 1CP NAME AND FUNCTION Output enable input (active LOW)
LOGIC SYMBOL
1 24
1OE 47
2OE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23
3-State flip-flop outputs Ground (0V) Positive supply voltage 3-State flip-flop outputs Output enable input (active LOW) Clock input Data inputs Data inputs Clock input
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 1CP 2CP
46 44 43 41 40 38 37 36 35 33 32 30 29 27 26
48
25
SW00075
LOGIC DIAGRAM
1D0 D CP FF1 Q 1Q0 2D0 D CP FF9 Q 2Q0
1CP 1OE
2CP 2OE
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
SW00076
FUNCTION TABLE
INPUTS OPERATING MODES nOE Load and read register Load register and disable outputs L L H H nCP nDx l h l h INTERNAL FLIP-FLOPS L H L H OUTPUTS Q0 to Q7 L H Z Z
H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition Z = high impedance OFF-state = LOW-to-HIGH CP transition
1998 Mar 17
3
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State)
74LVC16374A/ 74LVCH16374A
LOGIC SYMBOL (IEEE/IEC)
1OE 1CLK 2OE 2CLK 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 1 48 24 25 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 2D 2 1EN C1 2EN C2 1D 1 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
BUS HOLD CIRCUIT
VCC
Data Input
To internal circuit
SW00044
SW00077
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb tr, tf PARAMETER DC supply voltage (for max. speed performance) DC supply voltage (for low-voltage applications) DC input voltage range DC input voltage range; output HIGH or LOW state DC output voltage range; output 3-State Operating free-air temperature range Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS LIMITS MIN 2.7 1.2 0 0 0 -40 0 0 MAX 3.6 3.6 5.5 VCC 5.5 +85 20 10 UNIT V V V C ns/V
1998 Mar 17
4
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State)
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage; output HIGH or LOW state DC output voltage; output 3-State DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI t 0 Note 2 VO uVCC or VO t 0 Note 2 Note 2 VO = 0 to VCC CONDITIONS
74LVC16374A/ 74LVCH16374A
RATING -0.5 to +6.5 -50 -0.5 to +6.5 "50 -0.5 to VCC +0.5 -0.5 to 6.5 "50 "100 -65 to +150 500 500
UNIT V mA V mA V mA mA C
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIH HIGH level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V LOW level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V VCC = 2.7V; VI = VIH or VIL; IO = -12mA VO OH HIGH level output voltage VCC = 3 0V; VI = VIH or VIL; IO = -100A 100A 3.0V; VCC = 3.0V; VI = VIH or VIL; IO = -18mA VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100A VCC = 3.0V; VI = VIH or VIL; IO = 24mA II IOZ Ioff ICC ICC Input leakage current 3-State output OFF-state current Power off leakage supply Quiescent supply current Additional quiescent supply current per input pin VCC = 3.6V; VI = 5.5V or GND6 VCC = 3.6V; VI = VIH or VIL; VO = 5.5V or GND VCC = 0.0V; VI or VO = 5.5V VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC -0.6V; IO = 0 0.1 5 "0.1 0.1 VCC*0.5 VCC*0.2 02 VCC*0.6 VCC*0.8 0.40 0.20 0.55 "5 "5 "10 20 500 A A A A A V VCC V VCC 2.0 GND V 0.8 TYP1 MAX V UNIT
VIL
1998 Mar 17
5
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State)
74LVC16374A/ 74LVCH16374A
DC ELECTRICAL CHARACTERISTICS (Continued)
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN IBHL IBHH IBHLO IBHHO Bus hold LOW sustaining current Bus hold HIGH sustaining current Bus hold LOW overdrive current Bus hold HIGH overdrive current VCC = 3.0V; VI = 0.8V2, 3, 4 VCC = 3.0V; VI = 2.0V2, 3, 4 VCC = VCC = 3.6V2, 3, 5 3.6V2, 3, 5 75 -75 500 -500 TYP1 MAX A A A A UNIT
NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25C. 2. Valid for data inputs of bus hold parts (LVCH16-A) only. 3. For data inputs only, control inputs do not have a bus hold circuit. 4. The specified sustaining current at the data input holds the input below the specified VI level. 5. The specified overdrive current at the data input forces the data input to the opposite logic input state. 6. For bus hold parts, the bus hold circuit is switched off when Vi exceeds VCC allowing 5.5V on the input terminal.
AC CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500; Tamb = -40C to +85C. LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3V 0.3V MIN tPHL tPLH tPZH tPZL tPHZ tPLZ tW tsu th fmax Propagation delay CP to Qn 3-State output enable time OE to Qn 3-State output disable time OE to Qn CP pulse width HIGH or LOW Set-up time Dn to CP Hold time Dn to CP Maximum clock pulse frequency 1, 4 2, 4 2, 4 1 3 3 1 1.5 1.5 1.5 3.0 2.0 1.5 100 TYP1 3.8 3.6 3.9 1.5 0.3 -0.3 - MAX 5.4 5.6 5.5 - - - - VCC = 2.7V MIN 1.5 1.5 1.5 3.0 1.9 1.1 80 MAX 6.4 6.6 6.5 - - - - VCC = 1.2V MAX 17 20 12 - - - - ns ns ns ns ns ns MHz UNIT
NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25C.
1998 Mar 17
6
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State)
74LVC16374A/ 74LVCH16374A
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V VY = VOH -0.3V at VCC w 2.7V; VY = VOH - 0.1 VCC at VCC t 2.7V
VI 1/fMAX VI CP INPUT GND tw tPHL VM tPLH VI VM CP INPUT GND tsu th Dn INPUT tsu th VM
VOH Qn OUTPUT VOL
GND
SW00078
Waveform 1. Clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency
VI OE INPUT GND VM VM
VOH Qn OUTPUT
VOL
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
Waveform 3. Data set-up and hold times for the Dn input to the CP input
tPLZ VCC OUTPUT LOW-to-OFF OFF-to-LOW VOL
tPZL
TEST CIRCUIT
VCC VM S1 2VX
tPHZ VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled VY
tPZH
PULSE GENERATOR
outputs enabled
SWITCH POSITION TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH SWITCH Open 2SW00072
Waveform 2. 3-State enable and disable times
DEFINITIONS RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators.
SW00047
Waveform 4. Load circuitry for switching times
1998 Mar 17
7
EEEEEEE EEEE EE EE EEEEEEE EEEE EE EE EEEEEEE EEEE EE EE
VM VM
SW00079
Test Circuit for 3-State Outputs
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State)
74LVC16374A/ 74LVCH16374A
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
1998 Mar 17
8
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State)
74LVC16374A/ 74LVCH16374A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm
SOT362-1
1998 Mar 17
9
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State)
74LVC16374A/ 74LVCH16374A
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04534
Philips Semiconductors
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